高島　康裕／タカシマ　ヤスヒロ／Yasuhiro Takashima

所属	【学部】情報システム工学科【大学院】情報工学専攻　融合システムコース
役職/職名	教授
学位（授与機関）	博士(工学) (東京工業大学)
担当科目	コンピュータアーキテクチャ電気回路基礎・同演習確率論情報メディア工学実験第4 (FPGAによるシステム実装) 組み合わせ最適化論 (大学院)
略歴	1993年3月東京工業大学工学部電気・電子工学科卒業 1993年4月東京工業大学理工学研究科電気・電子工学専攻博士前期課程入学 1995年3月東京工業大学理工学研究科電気・電子工学専攻博士前期課程修了 1995年4月東京工業大学理工学研究科電気・電子工学専攻博士後期課程入学 1998年3月東京工業大学理工学研究科電気・電子工学専攻博士後期課程修了 1998年4月北陸先端科学技術大学院大学情報科学研究科助手 (-- 2003年3月) 1998年9月マイクロアーク株式会社技術指導アドバイザー (-- 2001年3月) 2003年4月北九州産業学術推進機構招聘研究員 (-- 2005年3月) 2003年4月北九州市立大学国際環境工学部情報メディア工学科客員助教授 (-- 2005年3月) 2005年4月北九州市立大学国際環境工学部情報メディア工学科助教授 (-- 2007年3月) 2007年4月北九州市立大学国際環境工学部情報メディア工学科准教授
専門分野	VLSI設計最適化，ハイパフォーマンスコンピューティング，FPGAシステム実装

業績紹介

VLSIレイアウト最適化

VLSIレイアウト最適化，具体的には，構成要素の位置を決定する配置問題，及び，その間の信号線の経路を決定する配線問題について，整数線形計画法(ILP)や充足判定問題(SAT)，制約充足問題(CSP)等に代表される厳密解法，Simulated Annealing (SA)等のメタヒューリスティック，Numerical Optimization等から，それぞれの問題に最も適した解法を模索しながら，高速，かつ，高性能な手法開発を目指しています．

学術論文

Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani,
`` Assignment of Intervals to Parallel Tracks with Minimun Total Cross-Talk,
IEICE Trans. on Fundamentals, Vol.E81-A, No.9, pp. 1909--1915, 1998.

Yukiko Kubo, Yasuhiro Takashima, Sigetoshi Nakatake, and Yoji Kajitani,
``Self-reforming Steiner Trees by Flip and Applications to VLSI Interconnection,''
Trans. of IPSJ, in Japanese, Vol.41, No.5, pp. 881-888, 2000.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani,
``Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints,''
IEICE Trans. on Fundamentals Vol.E87-A, No.12, pp. 3224-3232, 2004.

Takashi Nojima, Xiaoke Zhu Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani,
``A Device-Level Placement with Schema Based Clusters in Analog IC Layouts,''
IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp. 3258-3264, 2004.

Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, and Shigetoshi Nakatake,
``A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects,''
IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp. 3301-3308, 2004.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani,
``The Oct-Touched Tile: A New Architecture for Shape-Based Routing,''
IEICE Trans. on Fundamentals, Vol.E89-A, No.2, pp. 448-455, 2006.

Kunihiko Yanagibashi, Yasuhiro Takashima, and Yuichi Nakamura,
``A Relocation Method for Circuit Modifications,''
IEICE Trans. on Fundamentals, Vol.E90-A, No.12, pp. 2743--2751, 2007.

Syota Kuwabara, Yukihide Kohira, and Yasuhiro Takashima,
``An Effective Overlap Removable Objective for Analytical Placement,''
IEICE Trans. on Fundamentals, Vol.E96-A, No.6, pp. 1348-1356, 2013.

国際会議 <査読有り>

Yukiko Kubo, Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani,
``Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout,''
Proc. of ASP-DAC 2000, pp. 87-92, 2000.

Yasuhiro Takashima and Hiroshi Murata,
``SLASH: A Deterministic Block Placement Algorithm Based on Sequence-Pair,''
Proc. of APC-CAS 2000, pp. 825-828, 2000.

Yasuhiro Takashima and Hiroshi Murata,
``The Tight Upper Bound of the Empty Rooms in Floorplan,''
Proc. of SASIMI 2001, pp. 264-271, 2001.

Yasuhiro Takashima, Akira Kaneko, Shinji Sato, and Mineo Kaneko,
``Two-Dimensional Placement Method Based on Divide-and-Replacement,''
Proc. of APC-CAS 2002, pp. 341-346, 2002.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani,
``Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints,''
Proc. of ASP-DAC 2004, pp. 19-24, 2004.

Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani,
``Multi-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts,''
Proc. of ASP-DAC 2004, pp. 406-411, 2004.

Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani,
``A Device-Level Placement with Multi-Directional Convex Clustering,''
Proc. of ASP-DAC 2004, pp. 406-411, 2004.

Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, and Shigetoshi Nakatake,
``A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects,''
Proc. of ISCAS 2004, 2004.

Changwen Zhuang, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani,
An algorithm for checking slicing floorplan based on HPG and its applicatipon,''
Proc. of ICCCAS 2004, pp. 1223-1227, 2004.

Ning Fu, Shigetoshi NakatakeYasuhiro Takashima and Yoji Kajitani,
``The Oct-Touched Tile: A New Architecture for Shape-Based Routing,''
Proc. of GLSVLSI 2005, P1.13, 2005.

Tan Yan, Qing Dong, Yasuhiro Takashima, and Yoji Kajitani,
``How Does Partitioning Matter for 3D Floorplanning?,''
Proc. of GLSVLSI 2005, pp. 73-78, 2006.

Tan Yan, Shuting Li, Yasuhiro Takashima, and Hiroshi Murata,
``A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Block,''
Proc. of ASP-DAC 2007, pp. 268-273, 2007.

Kunihiko Yanagibashi, Yasuhiro Takashima, and Yuichi Nakamura,
``A Relocation Method for Circuit Modification,''
Proc. of MWSCAS 2007, pp. 783-786, 2007.

Shuting Li, Tan Yan, Yasuhiro Takashima, and Hiroshi Murata,
``Fast Wire Length Estimation in Obstructive Block Placement,''
Proc. of ICECS2008, pp. 654-657, 2008.

Naoto Funatsu and Yasuhiro Takashima,
``Overlap-aware Analytical Placement Based on Stable-LSE,''
Proc. of SASIMI 2009, pp. 318-323, 2009.

Masatomo Kuwano and Yasuhiro Takashima,
``Stable-LSE based Analytical Placement with Overlap Removable Length,''
Proc. of SASIMI 2010, pp. 115-120, 2010. (Outstanding Paper Award)

Syota Kuwabara, Yukihide Kohira, and Yasuhiro Takashima,
``An Effective Overlap Removable Objective for Analytical Placement,''
Proc. of SASIMI 2012, pp. 135-140, 2012.

Tieyuan Pan and Yasuhiro Takashima,
``A Fixed-Length Routing Method Based on the Color-Coding Algorithm,''
Proc. of SASIMI 2013, pp. 214-219, 2013.

Syota Kuwabara, Yukihide Kohira, and Yasuhiro Takashima,
``An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method,''
Proc. of ASICON 2013, C5-3, 2013.

Tieyuan Pan and Yasuhiro Takashima,
``A Randomized Algorithm for the Fixed-Length Routing Problem,
Proc. of APCCAS 2014, pp.711-714, 2014.

国際会議 <査読無し>

Yasuhiro Takashima,
``Analytical Placement for Rectilinear Blocks,
Proc. of ASP-DAC 2015, pp.220-225, 2015. (招待講演)

クロックタイミング・スケジューリング

デジタルシステムにおいて，クロック信号に伴なうタイミングは性能を決める大きな要素の一つです．本研究室では，クロック信号分配が設計時とはずれて製造されたときの修正方法や，処理時間が変化するときの処理順序等の最適化について，統計的な処理を利用しながら，研究を進めています．

学術論文

Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura,
``Post-silicon Clock-timing Tuning Based on Statistical Estimation,''
IEICE Trans. on Fundamentals, Vol.E91-A, No.9, pp. 2322--2327, 2008.

国際会議 <査読有り>

Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura,
``A Novel Clock Deskew Method by Linear Programming,''
Proc. of MWSCAS 2007, pp. 1261-1264, 2007.

Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura,
``Post-Silicon Clock-timing Tuning Based on Statistical Estimation,''
Proc. of SASIMI 2007, pp. 161-165, 2007.

Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura,
``Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests,''
Proc. of ISCAS 2010, pp. 1595-1598, 2010.

Seiya Nagatsuka and Yasuhiro Takashima,
``Sub-path delay estimation for reconvergent path,''
Proc. of APCCAS 2012, pp. 675-678, 2012.

Masatsugu Hosoki, Seiya Nagatsuka, and Yasuhiro Takashima,
``Delay Estimation Method for Correlated Net Delay Variations,
Proc. of APCCAS 2014, pp.747-750, 2014. (招待講演)

Komei Nomura, Yasuhiro Takashima, and Yuichi Nakamura,
``PEVaS: Power and Execution-Time Variation-Aware Scheduling for MPSoC,''
Proc. of NEWCAS 2016, K-1, 2014.

国際会議 <査読無し>

Yasuhiro Takashima, Takanobu Shiki, and Yuichi Nakamura,
``Statisitical Delay Estimation with Path-Delay Test,''
Proc. of VMC 2010, 2010.

Komei Nomura, Yasuhiro Takashima, and Yuichi Nakamura,
``PEVaS_recalc: Extention of PEVaS for MPSoC,''
Proc. of TJCAS 2016, S1A.6, 2016.

FPGA

VLSIの製造技術は依然として進歩し続けています．その一方で，設計は，これまでに考えてこなかったような新たな問題に直面し，設計時間の長大化が深刻な問題として取らえられています．この一つの解法として，製造後回路要素を変更可能な構成要素を規則的に配置することによって，チップ設計の時間を抑えつつ，システムを設計できるField-Programmable Gate Array(FPGA) が注目されています．我々は，このFPGAの構成の最適化の研究とともに，FPGAを用いたシステム全体の最適化についても取りくんでいます．

学術論文

Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani,
``Routability of FPGAs with Extremal Switch-Block Structures, ''
IEICE Trans. on Fundamentals, Vol.E81-A, No.5, pp. 850--856, 1998.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Yoji Kajitani,
``A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os,''
IEICE Trans. on Fundamentals, Vol.E90-A, No.5, pp. 924--931, 2007.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi,
``Optimal Time-multiplexing in inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems,''
IEICE Trans. on Fundamentals, Vol.E91-A, No.12, pp. 3539-3547, 2008.

Masato Inagi, Yasuhiro Takashima, and Yuichi Nakamura,
``Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems,''
IPSJ Trans. on System LSI Design Methodology, Vol.3, pp. 81--90, 2010.

Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, and Shin'ichi Wakabayashi,
``Inter-FPGA Routing for Partially Time-multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies,''
IEICE Trans. on Fundamentals, Vol.E98-A, No.12, pp. 2572-2583, 2015.

Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, and Yasuhiro Takashima,
``An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device,''
IEICE Trans. on Fundamentals, Vol.E99-A, No.7, pp. 1345-1354, 2016.

Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, and Takahiro Watanabe,
``An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device,''
IEICE Trans. on Fundamentals, in press, 2016.

国際会議 <査読有り>

Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani,
``Detailed-Routability of FPGAs with Extremal Switch-Block Structures,''
Proc. of ED & TC 1996, pp. 160-164, 1996.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Yoji Kajitani,
``A Performance-Driven Bipartitioning A Performance-Driven Bipartitioning Algorithm for Multi-FPGA Implementation with Time-Multiplexed I/Os,''
Proc. of FPT 2006, pp. 361-364, 2006.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi,
``ILP-Based Optimization of Time-Multiplexed I/O Assignment for Multi-FPGA Systems,''
Proc. of ISCAS 2008, pp. 1800-1803, 2008.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura,
``Evaluation of Introducing Multiple Time-multiplexing Degrees to Inter-FPGA Connections on Multi-FPGA Systems,''
Proc. of ITC-CSCC 2009, A-03-0650, 2009.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura,
``Globally Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Systems,''
Proc. of FPL 2009, pp. 212-217, 2009.

最適化手法

科学技術の目覚ましい進歩により，常に新しい技術や要望から派生する制約が出てくるため，問題が刻々と変化しています．そのため，その問題を解く最適化手法も常に変化し続ける必要があります．我々は，そのような社会のニーズに答えるべく，様々な最適化手法を研究しています．

国際会議 <査読有り>

Masato Shimomura and Yasuhiro Takashima,
``Application of Monte-Carlo Tree Search to Traveling-Salesman Problem,''
Proc. of SASIMI 2016, in press, 2016.

国際会議 <査読無し>

Yasuhiro Takashima, Shohei Mizutani, Kenji Hotta, Ryosuke Kohno, and Yuichi Nakamura,
``Application of Quadratic Placement Optimization to Proton Beam Therapy,''
Proc. of TJCAS 2015, p.18, 2015.

その他全業績

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