Shigetoshi NAKATAKE
| Title | Professor |
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| Degree | Doctor of Engineering | |
| Department | Department of Information and Systems Engineering | |
| nakatake[ at ]kitakyu-u.ac.jp ＊Please change "[at]" to "@". |
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| Education | 1992: B.E. from Tokyo Institute of Technology. 1994: M.S. from Japan Advanced Institute of Science and Technology. 1999: D.E. from Tokyo Institute of Technology. |
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| Employment History | 1997-1999: Research associate of Tokyo Institute of Technology. 1999-2000: Lecturer of Kitakyushu University. 2001-2011 : Associate professor of University of Kitakyushu. 2011- : Professor of University of Kitakyushu. |
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| Teaching Activities | Undergraduate: - Algorithms and data structures - Design of integrated circuits - Experiments of information and media engineering Graduate school; - VLSI physical designs - Practices of automotive LSI designs |
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| Research Interest | - Computer-aided design algorithms of integrated circuits - Mixed signal LSI design methodologies - Analog LSI design for manufacturability |
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| Publications | Recent papers (2006-2010): [Journals] (1) S. Nakatake, M. Kawakita, T. Ito, M. Kojima, M. Kojima, K. Izumi, T. Habasaki, ``Regularity-Oriented Analog Placement with Conditional Deisgn Rules'', IEICE Transaction on Fundamental of Electronics, Communications and Computer Sciences, Vol. E93-A, No.12, pp.2389-2398, Dec., (2010) (2) K. Kato, M. Endo, T. Inoue, S. Nakatake, M. Yamabe, S. Ishihara, ``Photomask Data Prioritization based on VLDI Design Intent and its Utilization for Mask Manufacturing'', in press, IEICE Transaction on Fundamental of Electronics, Communications and Computer Sciences, Vol. E93-A, No.12, pp.2424-2432, Dec., (2010) (3) B. Yang, S. Nakatake, ``Fast Shape Optimization of Metalization Patterns for Power-MOSFET'', IEICE Transaction on Fundamental of Electronics, ommunications and Computer Sciences, Vol. E92-A, No.12, pp.3052-3060, Dec., (2009) (4) Q. Dong, B. Yang, J. Ling, S. Nakatake, ``Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming'', IEICE Transaction on Fundamental of Electronics, Communications and Computer Sciences, Vol. E92-A, No.12, pp.3103-3110, Dec., (2009) (5) Q. Dong, S. Nakatake, ``Structured Placement with Topological Regularity Evaluation'', ISPJ Transaction on System LSI Design Methodology, Vol.2, pp.1-17, (2009) (6) B. Yang, H. Murata, S. Nakatake, ``A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion'', IEICE Transaction on Fundamental of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 2, pp.542-549, (2008) (7) N. Fu, S. Nakatake, Y. Takashima, Y. Kajitani, ``The Oct-Touched Tile: A New Architecture for Shape-Based Routing'', IEICE Trans. on Fundamentals of ECCS, Vol.E89-A, No.2, pp.448-455, Feb. (2006) [Conferences] (1) B. Liu, Q. Dong, B. Yang, J. Li, S. Nakatake, ``Layout-aware Mismatch Modeling for CMOS Current Sources with D/A Converter Analysis'', to appear in Proc. of IEEE ISQED, March, (2011) . (2) B. Yang, Q. Dong, J. Li, S. Nakatake,``Structured Analog Circuit Design and MOS Transistor Decomposition for High Accuracy Applications '', Proc. of IEEE/ACM ICCAD, pp.721-728, Nov., (2010). (3) T. Fujimura, B. Yang, Q. Dong, S. Nakatake,``Current-Driven Linear Layout of MOSFET with Diffusion-Sharing'', Proc. of IEEJ International Analog VLSI Workshop, pp.225-230, Sep., (2010) (4) S. Nakatake, M. Kawakita, T. Ito, Masahiro Kojima, Michiko Kojima, K. Izumi, T. Habasaki,``Regularity-Oriented Analog Placement with Diffusion Sharing and Well Island Generation'', Proc. of IEEE/ACM ASP-DAC, pp.305-311, Jan., (2010). (5) B. Liu, T. Fujimura, B. Yang, S. Nakatake, ``D-A Converter Based Variation Analysis for Analog Layout Design'', Proc. of IEEE/ACM ASP-DAC, pp.843-848, Jan., (2010). (6) Q. Dong, B. Yang, J. Li, S. Nakatake, ``Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming'', Proc. of ACM GLSVLSI'09, pp.413-416, (2009). (7) J. Li, B. Yang, X. Hu, Q. Dong, S. Nakatake, ``STI Stress Aware Placement Optimization Based on Geometric Programming'', Proc. of ACM GLSVLSI'09, pp.209-214, (2009). (8) S. Nakatake, Z. Karimi, T. Taghavi, M. Sarrafzadeh,``Block Placement to Ensure Channel Routability'',Proc. of ACM GLSVLSI'07, pp.465-468, (2007). (9) Q. Dong, S. Nakatake, ``Constraint-Free Analog Placement with Topological Symmetry Structure'', Proc. of IEEE/ACM ASP-DAC, pp.186-191, (2008). (10) B. Yang, S. Nakatake, H. Murata, ``Fast Shape Optimization of Metallization Patterns for DMOS Based Driver'', Proc. of IEEE ISQED, pp.617-620, (2008). (11) T. Fujimura, S. Nakatake, ``Transistor-Level Programmable MOS Analog IC with Body Biasing'', Proc. of IEEE ISCAS, pp.153-156, (2008). (12) S. Nakatake, ``Structured Placement with Topological Regularity Evaluation'', Proc. of IEEE/ACM ASP-DAC, p.215- 220, Jan., (2007). (13) K. Kida, T. Matsuo, T. Tashiro, S. Nakatake, ``Sequence-Pair Based Compaction under Equi-Length Constraint'', Proc. of IEEE APCCAS'06, p.1017-1020, Dec., (2006) (14) T. Nojima, S. Nakatake, T. Fujimura, K. Okazaki, Y. Kajitani, and N. Ono,``Adaptive Porting of Analog IPs with Reusable Conservative Properties'',Proc. of IEEE Computer Society ISVLSI'06, pp.18-23, Mar. (2006) (15) T. Yan, T. Nojima, S. Nakatake,``Formulating the Empirical Strategies in Module Generation of Analog MOS Layout'',Proc. of IEEE Computer Society ISVLSI'06, pp.44-49, Mar. (2006) (16) N. Fu, S. Nakatake, M. Mineshima,``Multi-SP: A Representation with United Rectangles for Analog Placement and Routing'',Proc. of IEEE Computer Society ISVLSI'06, pp.38-43, Mar. (2006) |
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| Other activities | Recent Projects: - "R&D of Mixed-signal LSI IP and its cutting-edge design technologies", Regional innovation cluster program Fukuoka cluster for advanced system LSI technology development (2007-2011). - Variation-tolerant analog LSI design methodology based on fine-grain transistor array, STARC (2007-2009). - Performance- and manufacturability-aware analog macro synthesis based on transistor array, STARC (2010-2012). |
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